Conventionally, a high-voltage integrated circuit (HVIC) has been proposed that achieves a level shift circuit without using a photocoupler. For example, such a HVIC includes a high-breakdown-voltage laterally diffused metal-oxide semiconductor transistor (LDMOS) for level shifting. As disclosed, for example, in US 2006/0249807 corresponding to JP-A-2006-313828, in a high-breakdown-voltage LDMOS, a drain region is placed in the center, and a source region is placed around the periphery of the drain region. Thus, the source region is concentrically arranged with respect to the drain region to eliminate a singular point. In such an approach, an electric current almost uniformly flows so that the LDMOS can have a high breakdown voltage.
FIG. 16 is a diagram illustrating a cross-sectional view of such a LDMOS. An n-type well region J2 and an n+-type contact region J3 are formed in an n−-type drift layer J1. The n-type well region J2 and the n+-type contact region J3 construct a drain region. A p-type channel region J4 and an n+-type source region J5 are formed around the drain region. A drain wiring J6 is formed on a surface of the n+-type contact region J3. A source wiring J7 is formed on a surface of the n+-type source region J5. Since the drain region is surrounded by the n+-type source region J5, the drain wiring J6 passes above the source wiring J7 when being pulled outside the source wiring J7.
An interlayer insulation film J8 is interposed between the drain wiring J6 and the source wiring J7 for electrical insulation between the drain wiring J6 and the source wiring J7. Typically, in a high-breakdown-voltage LDMOS for level shifting, a potential of 0 volt is applied to the source wiring J7, and a potential of from about 600 volts to about 1200 volts is applied to the drain wiring J6. That is, a voltage of from about 600 volts to about 1200 volts is applied to the interlayer insulation film J8, which is interposed between the drain wiring J6 and the source wiring J7. Therefore, the thickness of the interlayer insulation film J8 needs to be large enough to prevent breakdown of the interlayer insulation film J8. However, it takes a long time to form an interlayer insulation film that has a large thickness.
FIG. 17 is a diagram illustrating a potential distribution in the LDMOS. As can be seen from FIG. 17, in the n−-type drift layer J1, the potential distribution is uniform around the n-type well region J2. However, in the interlayer insulation film J8 and a LOCOS oxide film J9 located below the drain wiring J6, the potential distribution is nonuniform. The nonuniform potential distribution indicates that an electric field concentration occurs due to a high potential of the drain wiring J6. The electric field concentration may result in breakdown of the interlayer insulation film J8 and the LOCOS oxide film J9.
The problems described above can arise other types of high-breakdown-voltage transistors such as an insulated gate bipolar transistor (IGBT) and a bipolar transistor.